1. Field of the Invention
The present disclosure relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for an in-plane switching mode liquid crystal display device and a method of manufacturing the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, however, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as substitutes for the CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
The LCD device using an electric field induced in a vertical direction has disadvantage in viewing angles. To solve this problem, an in-plane switching (IPS) mode LCD device using an in-plane electric field is proposed.
FIG. 1 is a schematic cross-sectional view illustrating an IPS mode LCD device according to a related art.
Referring to FIG. 1, the IPS mode LCD device includes an array substrate 10, a color filter substrate 9 and a liquid crystal layer 11. The array substrate 10 includes pixel and common electrodes 30 and 17 alternately arranged to produce an in-plane electric field L. The liquid crystal layer 11 is operated by the electric field L.
FIGS. 2A and 2B are schematic views illustrating operations in ON and OFF states, respectively, of the IPS mode LCD device according to the related art.
Referring to FIG. 2A, in the ON state, alignment of liquid crystal molecules 11a right over the pixel and common electrodes 30 and 17 is not changed while alignment of liquid crystal molecules 11b over a region between the pixel and common electrodes 30 and 17 is changed and aligned along the electric field L. In other words, since the liquid crystal molecules 11a and 11b are operated by the in-plane electric field L, viewing angles is widened. Accordingly, the IPS mode LCD device has wide viewing angles of about 80 degrees to about 89 degrees in up/down/right/left directions. Herein and hereafter, “/” refers to “and”.
Referring to FIG. 2B, in the OFF state, an in-plane electric field is not induced between the pixel and common electrodes 30 and 17, and arrangement of the liquid crystal molecules 11a and 11b is not changed.
FIG. 3 is a cross-sectional view illustrating a pixel region of the IPS mode LCD device according to the related art.
Referring to FIG. 3, a gate insulating layer 48 is formed on a substrate 40, a data line 50 is formed on the gate insulating layer 48, a passivation layer 60 is formed on the data line 50, and pixel and common electrodes 64 and 62 are formed on the passivation layer 60. The pixel and common electrodes 64 and 62 alternate in a pixel region P.
Although not shown in the drawings, a gate line and a common line are formed below the gate insulating layer 48, and a thin film transistor is formed near the crossing portion of the gate line and the data line 50. The gate line and the data line 50 define the pixel region P. The thin film transistor includes a gate electrode, a semiconductor layer, and source and drain electrodes.
The pixel electrode 64 is connected to the drain electrode, and the common electrode 62 is connected to the common line. The pixel and common electrodes 64 and 62 have a bar shape.
The pixel and common electrodes 64 and 62 are formed with a single-layered structure using a transparent conductive material or an opaque metal. In this structure, an ambient contrast ratio is decreased because of the high light reflectance for ambient light.
Furthermore, the pixel and common electrodes 64 and 62 each have a width of about 2.2 μm or more. Such the width is caused by resolution limit of a light exposure apparatus which is used in a pattering process.
In more detail, in order to form and pattern a metal layer or semiconductor layer on a substrate, a photoresist layer is formed on the metal layer or semiconductor layer, then light exposure is performed using a light exposure apparatus, then the photoresist layer is developed to form a photoresist pattern having a predetermined width, and then the metal layer or semiconductor layer is etched using the photoresist pattern as an etching mask, thereby forming a metal pattern or semiconductor pattern.
At the current level of the art, a photoresist pattern having a width of about 3.1 μm or less cannot be stably realized because of resolution limit of the light exposure apparatus. Accordingly, the photoresist pattern should have a width of at least 3.1 μm.
When a metal layer or semiconductor layer is etched using the photoresist patter of at least 3.1 μm, even though an over-etching is conducted, limit of a side etch bias is 0.9 μm and a metal pattern or semiconductor pattern having a width of about 2.2 μm or less cannot be formed thus. The etch bias means an amount of width of a layer that is inward removed with respect to side edges of the photoresist layer.
Because of the patterning restriction, the pixel and common electrodes of the related art have a width of about 2.2 μm or more.
Aperture ratio of a pixel region is defined as a ratio of a total region of the pixel region to a region except for a region of the pixel region that is blocked by elements in the pixel region. However, in the related art, width of the pixel and common electrodes cannot be further reduced. Accordingly, this is problematic in improvement of brightness and low power consumption.